Generally, a pitch of a semiconductor device is shortened in accordance with a decreasing design rule, such that a channel length of a transistor is considerably reduced. To accommodate a decrease in the gate length below 0.13 μm, many efforts are being made to research and develop a shallow junction and super steep channel doping. Low energy implantation is currently performed for shallow junctions, which lowers the throughput of the manufacturing process.
FIG. 1 is a cross-sectional illustration of a prior art CMOS transistor. Referring to FIG. 1, the junction of a deep, sub-micron transistor is formed in the following manner. First, after a gate pattern has been formed, a sidewall oxide layer is deposited to have a thickness of about 20 Å thick.
LDD ion implantation is then performed at a low energy of about 2˜5 KeV to form the shallow junction of a PMOS transistor. Since the ion implantation energy is low, the dopant profile throughput of the equipment is lowered, which reduces the process margin.
Moreover, since the junction is made shallow to suppress lateral diffusion, junction loss in salicidation is increased, which, in turn, increases the drain leakage current of the transistor. Additionally, the transistor process margin is lowered by the short channel effect which is attributable to lateral diffusion of the impurities.
In the case of a PMOS transistor, a halo structure having a higher impurity density than the well is provided in the vicinity of the source/drain to prevent the depletion areas of the source and drain from closely approaching each other in a horizontal direction. As a result, the depletion areas of the source/drain are shortened and the performance of the PMOS transistor is lowered.
Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.